test: RG-A Sp18 6.4 GeV rebuild-scalers with 125MHz clock and generalized clock rollover correction

[c-dilks]

do not merge

This is for preserving the fixes we know are needed for the FC charge for RG-A Spring 2018 6.4 GeV data; more fixes and studies may be needed.

Fixes

1. generalized clock rollover correction
   • separates gated and ungated clock corrections
   • accounts for step-ups of ~2³² counts (original rollover correction only corrects step-downs)
   • does not assume the step size is 2³² (though perhaps we should assume this, actually)
2. we have fit the clock counts vs. timestamp and determined the DSC2 clock frequency was 125 MHz for most 6.4 GeV runs (see below)
   • the charge is calculated using a hard-coded clock frequency of 125 MHz

See also #1116

Clock Frequencies

run  gated   ungated
---  -----   -------
3031 85.0613 87.9861
3036 105.197 108.704
3037 88.6238 92.3011
3038 111.833 114.652
3048 67.1008 74.8741
3049 54.6598 58.9931
3050 113.333 124.878
3051 113.617 124.885
3052 116.11  124.874
3060 99.8533 122.867
3061 121.758 124.876
3063 120.068 124.873
3064 115.691 124.872
3065 116.811 124.878
3083 112.302 124.402
3087 115.264 124.875
3105 120.941 124.881
3820 116.593 124.872
3822 118.102 124.872
3827 113.382 124.881
3834 119.726 124.867
3839 120.865 124.874
3841 118.942 124.877
3842 119.552 124.874
3843 122.162 124.867
3845 120.322 124.872
3846 122.366 124.866
3847 120.262 124.873
3848 120.741 124.869
3849 120.474 124.875
3850 118.252 124.878
3851 122.605 124.869
3852 119.853 124.874
3853 119.05  124.877
3855 122.028 124.872
3856 123.003 124.873
3857 122.75  124.875