Discussions

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  OutOfMemoryError when loading large EDIF netlist

  BittuChan asked Apr 10, 2026 in Q&A · Closed · Answered

  

  

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  Agentic Development in Python

  coherent17 started Mar 28, 2026 in General

  

  

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  Other input for RapidWright for logical netlist rather than EDIF format

  coherent17 started Mar 6, 2026 in General

  

  

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  RapidWright Placer

  coherent17 started Nov 25, 2025 in General

  

  

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  RWRoute and routethru-s

  eddieh-xlnx started Sep 16, 2022 in General · Closed

  

  

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  Gradle JavaExec task fails in IntelliJ due to missing restoreScripts dependency.

  Han-sok started Sep 3, 2025 in General · Closed

  

  

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  Inter-site routing issues when routing DCP containing Processor System Reset block (proc_sys_reset)

  chrmarlyn asked Aug 28, 2025 in Q&A · Unanswered

  

  

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  Issues with intra-site routing on Versal board

  chrmarlyn asked Jul 7, 2025 in Q&A · Unanswered

  

  

  

  

  29
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  Issue with connecting previously removed cell pins to net

  chrmarlyn asked Jun 30, 2025 in Q&A · Answered

  

  

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  Underestimated Delay in reportTimingExample When Path Crosses HDIO or GTY Columns

  gigaAlter asked Jun 29, 2025 in Q&A · Unanswered

  

  

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  get_pblocks in RapidWright

  coherent17 asked Jun 26, 2025 in Q&A · Answered

  

  

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  Invoke RapidWright from Vivado

  coherent17 asked Jun 20, 2025 in Q&A · Closed · Unanswered

  

  

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  Bottom-up implementation? (divide and conquer)

  alexisfrjp asked May 12, 2025 in Q&A · Unanswered

  

  

  

  

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  How to Generate Vivado-like Timing Report and Extract Routing Mux Delays in RapidWright?

  gigaAlter asked Jun 6, 2025 in Q&A · Answered

  

  

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  Re-routing nets

  sma-asghar started May 23, 2025 in General

  

  

  

  

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  Routing Heat Map

  eddieh-xlnx started May 7, 2025 in General · Closed

  

  

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  Support for Custom Properties

  nicolaimueller asked Apr 30, 2025 in Q&A · Answered

  

  

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  fully route design report site pin not routed in RapidWright

  coherent17 asked Apr 3, 2025 in Q&A · Closed · Answered

  

  

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  get route fail net in rapidwright

  coherent17 asked Feb 25, 2025 in Q&A · Closed · Answered

  

  

  

  

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  Extract cell connections

  Licheng-Guo asked Aug 15, 2023 in Q&A · Closed · Unanswered

  

  

  

  

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  Routing congestion calculation

  coherent17 asked Feb 11, 2025 in Q&A · Answered

  

  

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  Creating Empty PBlocks in a .DCP for Future Noise Logic Insertion

  EirGalid asked Feb 5, 2025 in Q&A · Unanswered

  

  

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  Initialization of LUT value and Port Connection on my RW design

  alimousios98x asked Feb 1, 2025 in Q&A · Unanswered

  

  

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  How to estimate accurate utilization of LUTL from synthesized netlist in RapidWright?

  wengwz asked Nov 24, 2024 in Q&A · Unanswered

  

  

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  How to create a new Design from EDIFCellInst?

  wengwz asked Nov 8, 2024 in Q&A · Unanswered

  

  

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