ci: add RVV CI using cloud-v runner#377
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…itelist Currently, `cpu_features.cc` assumes any non-ARM architecture is x86/x64, which leads to a fatal missing `<cpuid.h>` error on architectures like RISC-V. This commit refactors the preprocessor macros to explicitly whitelist x86 architectures (`__x86_64__`, `__i386__`, `_M_X64`, `_M_IX86`). All other architectures (RISC-V, ARM, etc.) will now safely fall back to the default zero-initialization, allowing cross-compilation to succeed. Signed-off-by: ihb2032 <hebome@foxmail.com>
Introduce the RISC-V CI runner provided by the RISE project. This enables automated testing and building for the RISC-V architecture. Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
… without isolation On RISC-V runners, pip install ninja==1.11.1 falls back to source build and fails due to missing cmake module in the isolated build environment. Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
Signed-off-by: ihb2032 <hebome@foxmail.com>
Introduce the RISC-V CI runner provided by the RISE project. This enables automated testing and building for the RISC-V architecture. Signed-off-by: ihb2032 <hebome@foxmail.com>
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Description
Add RVV CI support using cloud-v runner to improve RISC-V vector instruction testing.
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